PIC16F87-E/ML【PDF 3/200 页】IC MCU FLASH 4KX14 EEPROM 28QFN

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100

8008H–AVR–04/11

ATtiny48/88

12.8.1

Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM1x[1:0] bits differently in normal, CTC, and PWM

modes. For all modes, setting the COM1x[1:0] = 0 tells the Waveform Generator that no action

on the OC1x Register is to be performed on the next compare match. For compare output

actions in the non-PWM modes refer to Table 12-2 on page 110. For fast PWM mode refer to

Table 12-3 on page 110, and for phase correct and phase and frequency correct PWM refer to

Table 12-4 on page 111.

A change of the COM1x[1:0] bits state will have effect at the first compare match after the bits

are written. For non-PWM modes, the action can be forced to have immediate effect by using

the FOC1x strobe bits.

12.9

Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the combination of the Waveform Generation mode (WGM1[3:0]) and Compare Out-

put mode (COM1x[1:0]) bits. The Compare Output mode bits do not affect the counting

sequence, while the Waveform Generation mode bits do. The COM1x[1:0] bits control whether

the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-

PWM modes the COM1x[1:0] bits control whether the output should be set, cleared or toggle at

a compare match (See “Compare Match Output Unit” on page 99.)

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 107.

12.9.1

Normal Mode

The simplest mode of operation is the Normal mode (WGM1[3:0] = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the

BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in

the same timer clock cycle as the TCNT1 becomes zero. The TOV1 Flag in this case behaves

like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow

interrupt that automatically clears the TOV1 Flag, the timer resolution can be increased by soft-

ware. There are no special cases to consider in the Normal mode, a new counter value can be

written anytime.

The Input Capture unit is easy to use in Normal mode. However, observe that the maximum

interval between the external events must not exceed the resolution of the counter. If the interval

between events are too long, the timer overflow interrupt or the prescaler must be used to

extend the resolution for the capture unit.

The Output Compare units can be used to generate interrupts at some given time. Using the

Output Compare to generate waveforms in Normal mode is not recommended, since this will

occupy too much of the CPU time.

12.9.2

Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM1[3:0] = 4 or 12), the OCR1A or ICR1 Register

are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when

the counter value (TCNT1) matches either the OCR1A (WGM1[3:0] = 4) or the ICR1

(WGM1[3:0] = 12). The OCR1A or ICR1 define the top value for the counter, hence also its res-

olution. This mode allows greater control of the compare match output frequency. It also

simplifies the operation of counting external events.

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